๋ณธ๋ฌธ ๋ฐ”๋กœ๊ฐ€๊ธฐ

๐“ก๐“ธ๐“ธ๐“ถ5: ๐’ฆ๐‘œ๐“‡๐‘’๐’ถ ๐’ฐ๐“ƒ๐’พ๐“‹/Computer Architecture(COSE222)

[์ปดํ“จํ„ฐ๊ตฌ์กฐ] CH4. RISC-V & RISC-V Instruction #2

CPU and Memory

1. ์™œ CPU๊ฐ€ memory์— ์ ‘๊ทผํ•ด์•ผ ํ•˜๋Š”๊ฐ€!

  • ์ฒ˜์Œ์—” ๋ชจ๋“  ์ฝ”๋“œ์™€ ๋ฐ์ดํ„ฐ๋“ค์ด ๋ฉ”์ธ ๋ฉ”๋ชจ๋ฆฌ์— ์ €์žฅ๋˜์–ด ์žˆ๋‹ค
  • CPU๋Š” ์ด ํ”„๋กœ๊ทธ๋žจ์„ ์‹คํ–‰์‹œํ‚ค๊ธฐ ์œ„ํ•ด์„œ ๋ฉ”์ธ ๋ฉ”๋ชจ๋ฆฌ์— access(read/write) ํ•ด์•ผ ํ•œ๋‹ค.
  • ์ •๋ฆฌํ•˜์ž๋ฉด access ํ•˜๋Š” ๋ชฉ์ ์—๋Š” ๋‹ค์Œ๊ณผ ๊ฐ™์€ ๋‘ ์ด์œ ๊ฐ€ ์žˆ๋‹ค.
    1. Instruciton read : CPU๊ฐ€ memory๋กœ ๋ถ€ํ„ฐ instructions์„ ์ฝ๋Š”๋‹ค
    2. Data read/write : CPU๊ฐ€ memory๋กœ ๋ถ€ํ„ฐ ๋ฐ์ดํ„ฐ๋ฅผ ์ฝ๊ฑฐ๋‚˜, memory์— ๋ฐ์ดํ„ฐ๋ฅผ ์“ด๋‹ค.

2. Instruction Access(Read)

CPU๋Š” ๋ฉ”์ธ ๋ฉ”๋ชจ๋ฆฌ์—์„œ instruction ์„ ์–ด๋–ป๊ฒŒ ์ฝ์–ด๋“ค์ด๋Š”๊ฐ€

  1. ๋ชจ๋“  CPU๋Š” ํ˜„์žฌ ์‹คํ–‰์ค‘์ธ instruction์˜ ์œ„์น˜, ์ฃผ์†Œ๋ฅผ ๊ณ„์† ์ถ”์ ํ•˜๋Š” ํŠน๋ณ„ํ•œ register๊ฐ€ ์žˆ๋‹ต๋‹ˆ๋‹ค!
    • ๊ทธ์˜ ์ด๋ฆ„์€ ๋ฐ”๋กœ๋ฐ”๋กœ Program Counter(PC)
      (x86 ์—์„œ๋งŒ ์˜ˆ์™ธ์ ์œผ๋กœ IP(instruction pointer) ๋ผ๋Š” ๋‹จ์–ด๋ฅผ ์”€
    • RISC-V ์—ญ์‹œ CPU ์•ˆ์— PC๋ผ๊ณ  ๋ถˆ๋ฆฌ๋Š” 32-bit์˜ ํŠน๋ณ„ํ•œ ๋ ˆ์ง€์Šคํ„ฐ๋ฅผ ๊ฐ€์ง€๊ณ  ์žˆ๋‹ค.
  2. PC๋Š” resetํ•  ๋•Œ๋งˆ๋‹ค ๋ฏธ๋ฆฌ ์ง€์ •๋œ ์ฃผ์†Œ๋กœ ์ดˆ๊ธฐํ™”๋œ๋‹ค.
    • x86์€ ์ฒซ๋ฒˆ์งธ instruction์˜ ์œ„์น˜๊ฐ€ 0xFFFF_FFF0์ž„
    • ARM์€ 0x0000_0000
    • RISC-V๋Š” ๊ตฌํ˜„ํ•˜๋Š” ์‚ฌ๋žŒ์ด ์ •์˜ํ•จ ; ์šฐ๋ฆฐ PC๋ฅผ 0x0000_0000์œผ๋กœ ์„ธํŒ…ํ•  ๊ฒƒ!
  3. PC๋Š” instruction์ด ํ•˜๋‚˜์”ฉ ์‹คํ–‰๋  ๋•Œ๋งˆ๋‹ค update ๋œ๋‹ค.

  • PC๊ฐ€ 0x0000 ๋ถ€ํ„ฐ 4์”ฉ ์ฆ๊ฐ€ํ•ด๊ฐ€๋ฉฐ memory์˜ instruction์„ ์ฐจ๋ก€๋Œ€๋กœ ์ฝ์–ด๋‚˜๊ฐ„๋‹ค.

3. Data Read/Write

  1. Main Memory ์•ˆ์— ์ฝ”๋“œ์™€ ๋ฐ์ดํ„ฐ๊ฐ€ ์ €์žฅ๋˜์–ด์žˆ๋‹ค.
    EX) int a, b, c; int dummy[100];
  2. CPU๋Š” ์ œํ•œ๋œ ๊ฐœ์ˆ˜์˜ ๋ ˆ์ง€์Šคํ„ฐ๋งŒ์„ ๊ฐ€์ง€๊ณ  ์žˆ๋‹ค.
    • RV32I์˜ ๊ฒฝ์šฐ 32๊ฐœ์˜ ๋ ˆ์ง€์Šคํ„ฐ๊ฐ€ ์žˆ๋‹ค
    • ๋”ฐ๋ผ์„œ CPU๋Š” ์–ด๋Š ์ •๋„ ์ •ํ•ด์ง„ ์–‘๋งŒ ๋ ˆ์ง€์Šคํ„ฐ์— ์ฆ‰์‹œ ์ €์žฅํ•  ์ˆ˜ ์žˆ๋‹ค.
  3. ๋”ฐ๋ผ์„œ ๋ชจ๋“  ์ •๋ณด๋ฅผ ๋ ˆ์ง€์Šคํ„ฐ์—์„œ ์ฒ˜๋ฆฌํ•  ์ˆ˜ ์—†์œผ๋ฏ€๋กœ,
    CPU๋Š” ๋ฉ”๋ชจ๋ฆฌ์™€ ๋ ˆ์ง€์Šคํ„ฐ ๊ฐ„์— ๋ฐ์ดํ„ฐ๋ฅผ ์ „์†กํ•˜๋Š” instruction์„ ์ œ๊ณตํ•ด์•ผ ํ•œ๋‹ค.

4. Word

  • ์–ด๋–ค ํŠน์ •ํ•œ ์ปดํ“จํ„ฐ ๋””์ž์ธ์— ์˜ํ•ด ์‚ฌ์šฉ๋˜๋Š” ํ•˜๋‚˜์˜ ๋ฐ์ดํ„ฐ์˜ ๋‹จ์œ„
  1. word๋Š” ํ•œ ๋ฒˆ์— ํ•จ๊ป˜ ์ฒ˜๋ฆฌ๋˜๋Š”, ์–ด๋–ค ๊ณ ์ •๋œ ํฌ๊ธฐ์˜ bit๋“ค์˜ ๊ทธ๋ฃน์ด๋‹ค.
  2. ์ด word์˜ ํฌ๊ธฐ, ์ฆ‰ bits์˜ ๊ฐœ์ˆ˜๋Š” ์ปดํ“จํ„ฐ ๊ตฌ์กฐ๋งˆ๋‹ค ๋‹ค๋ฅด๋‹ค.
    • word์˜ ํฌ๊ธฐ๋Š” ์ปดํ“จํ„ฐ์˜ ๊ตฌ์กฐ์™€ ์ž‘๋™์— ์žˆ์–ด์„œ ๋งŽ์€ ๋ถ€๋ถ„์— ๋ฐ˜์˜๋œ๋‹ค.
    • ๋ณดํ†ต ์ปดํ“จํ„ฐ์— ์žˆ๋Š” ๋ ˆ์ง€์Šคํ„ฐ์˜ ํฌ๊ธฐ๋Š” word์˜ ํฌ๊ธฐ์ž„
    • ํ˜„์žฌ ์ปดํ“จํ„ฐ์˜ word ํฌ๊ธฐ๋Š” ์ผ๋ฐ˜์ ์œผ๋กœ 32bit ๋˜๋Š” 64bit!!
  3. RV32I์˜ ๊ฒฝ์šฐ word ํฌ๊ธฐ๊ฐ€ 32bits! (4bytes)
  4. x86 ์˜ ๊ฒฝ์šฐ 64-bit CPU ๊ธฐ๋ฐ˜ ์ปดํ“จํ„ฐ์ž„์—๋„ ๋ถˆ๊ตฌํ•˜๊ณ , word ํฌ๊ธฐ๋Š” ํ˜ธํ™˜์„ฑ ๋ฌธ์ œ ๋•Œ๋ฌธ์— ์—ฌ์ „ํžˆ 16-bit๋ฅผ ์‚ฌ์šฉํ•œ๋‹ค.
  5. Alignment Restriction : ๋‹จ์–ด์˜ ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ๋Š” ํ•ญ์ƒ natural word boundaries ์œ„์— ์žˆ์–ด์•ผ ํ•จ (RV32I์˜ ๊ฒฝ์šฐ 4์˜ ๋ฐฐ์ˆ˜)
    • ์˜ˆ๋ฅผ ๋“ค์–ด ๋‹จ์–ด์— ์ ‘๊ทผํ•˜๊ธฐ ์œ„ํ•ด ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ๋ฅผ ์“ด๋‹ค๋ฉด 0x0000_0000, 0x0000_1004 ๊ฐ™์ด 4์˜ ๋ฐฐ์ˆ˜์—ฌ์•ผ ์ •์ƒ์ ์ธ ์ ‘๊ทผ ๊ฐ€๋Šฅ

Memory Address

  • ๊ธฐ๋ณธ์ ์œผ๋กœ CPU๋Š” byte ๋‹จ์œ„๋กœ ์ ‘๊ทผ์ด ๊ฐ€๋Šฅํ•˜๋‹ค (bit ๋‹จ์œ„ ์ ‘๊ทผ์€ ์•ˆ๋จ) = load byte = lb instruction
  • ๊ทธ๋ฆฌ๊ณ  ํ•œ ๋‹จ์–ด๊ฐ€ 4byte์ž„ -> ๋‹จ์–ด์˜ ์ฃผ์†Œ๋ฅผ 2์ง„์ˆ˜๋กœ ๋ณ€ํ™˜ํ•œ ๋’ค ์˜ค๋ฅธ์ชฝ์œผ๋กœ 2๋ฒˆ shift ํ•ด์ฃผ๋ฉด ๋ช‡ ๋ฒˆ์งธ ๋‹จ์–ด์ธ์ง€ ์•Œ ์ˆ˜ ์žˆ์Œ!
    (์™œ๋ƒ, ์ € ๋น„ํŠธ shift = ๋‚˜๋ˆ„๊ธฐ 4์ž„)
  • bit ๋‹จ์œ„๋กœ ์ ‘๊ทผํ•˜๊ณ  ์‹ถ๋‹ค๋ฉด byte ๋ฅผ ์ฝ์–ด์„œ and operation ํ•˜๊ธฐ

Memory Access Instruction

1. lw (= load words)

: memory๋กœ๋ถ€ํ„ฐ 32bit word๋ฅผ ์ฝ์–ด์„œ register๋กœ loads

  • I type instruction

lw rd, address

lw t0, 24(s3)
#t0 <= [s3 + 24]
#s3๋Š” memory์˜ ์ฃผ์†Ÿ๊ฐ’

๋งŒ์•ฝ s3 = 0x0000_0094 ์˜€๋‹ค๋ฉด
s3 + 24 = 0x0000_00ac

( ์ด ๋‘˜์˜ ๊ณ„์‚ฐ์€ ALU์—์„œ ์•Œ์•„์„œ ํ•ด์คŒ )

๊ทธ๋Ÿผ ์ด์ œ CPU์—์„œ address bus๋กœ 0x0000_00ac๋ฅผ memory์— ๋ณด๋‚ด๊ณ ,
0x0000_00ac ์ฃผ์†Ÿ๊ฐ’์— ์žˆ๋Š” ๋‹จ์–ด๋ฅผ ์ฝ์–ด์„œ Data bus์— ๋‹ด์•„ CPU์— ๋‹ค์‹œ ๋Œ๋ ค๋ณด๋‚ธ๋‹ค

๊ทธ๋Ÿผ ์ด ๋ฉ”๋ชจ๋ฆฌ์— ์žˆ๋˜ ๋‹จ์–ด๋ฅผ CPU๊ฐ€ ๋ฐ›์•„์„œ t0 ๋ ˆ์ง€์Šคํ„ฐ์— ์ €์žฅํ•˜๋Š” ๊ฒƒ!

  • ์—ฌ๊ธฐ์„œ s3๊ฐ€ base, 24๊ฐ€ offset ์ธ๋ฐ, ์ด offset์€ -2048 ๋ถ€ํ„ฐ +2047 ๊นŒ์ง€ ๊ฐ€๋Šฅํ•˜๋‹ค. (12-bit 2's complement)

2. sw (= store words)

: register์— ์žˆ๋Š” ๋‹จ์–ด๋ฅผ main memory์— store (write)

  • S type instruction

sw rs2, address

sw t2, 8(s3) 
# [s3 + 8] <= t2
#lw๋ž‘ ๋ฐ˜๋Œ€

Byte, Half-word Load/Store

ํ•œ ๋ฒˆ์— word๋‹จ์œ„๊ฐ€ ์•„๋‹Œ byte๋‚˜ half-word ๋‹จ์œ„๋กœ load๋‚˜ store์„ ํ•˜๊ณ  ์‹ถ๋‹ค๋ฉด ๋‹ค์Œ๊ณผ ๊ฐ™์€ instruction์ด ์žˆ๋‹ค.

lb : load byte
lh : load half-words (16bit)
lbu : load byte unsigned number
lhu : load half-words unsigned number
sb : store byte
sh : store half-words

3. lb

: memory์— ์žˆ๋Š” ํ•œ byte(=8bit)๋ฅผ register๋กœ load

  • I type instruction

lb rd, address

lb t0, 1(s3)
# t0 <= [s3 + 1]

์ž ๊น!!!!
register์€ 32 bit์ž–์•„ ๊ทธ๋Ÿผ 4 bit๋งŒ ๊ฐ€์ ธ์˜ค๋ฉด ์•ž์—” ์–ด๋–กํ•ด??!!?!

๊ทธ๋Ÿด ๋•Œ ์“ฐ๋Š”๊ฒŒ ๋ฐ”๋กœ Sign-extended
๋งจ ์™ผ ์ชฝ bit(MSB ; Most Significant Bit) ๋ฅผ ์•ž์œผ๋กœ ์ญ‰ ํ™•์žฅํ•ด์„œ ๋ ˆ์ง€์Šคํ„ฐ์— ๋ถ™์—ฌ๋„ฃ์–ด์ค€๋‹ค.
์ฆ‰ ๋ ˆ์ง€์Šคํ„ฐ ๋งจ ์˜ค๋ฅธ์ชฝ์— (LSB ; Least Significant Bit) ๊ฐ€์ ธ์˜ค๊ณ ์ž ํ–ˆ๋˜ byte๋ฅผ ๋„ฃ๊ณ  ๊ทธ ์•ž์— ๋น„๋Š” ๋ถ€๋ถ„์„
Sign-extended ํ•ด์„œ ์ฑ„์›Œ์ฃผ๋Š” ๊ฒƒ!

์ด sign-extended๋ฅผ ์จ์•ผ ์Œ์ˆ˜๋“ค๋„ ๊ทธ๋Œ€๋กœ ๋ณด์กด๋œ๋‹ค.

ex) FF(= 1111 1111)๋Š” ์•ž์— FFFFFF๋ฅผ ์ถ”๊ฐ€ํ•ด๋„ ์—ฌ์ „ํžˆ -1 !
02๋Š” ์•ž์— 000000๋ฅผ ์ถ”๊ฐ€ํ•ด๋„ ์—ฌ์ „ํžˆ 2 !

๋งŒ์•ฝ Sign-extended๋ฅผ ์“ฐ๊ณ  ์‹ถ์ง€ ์•Š๋‹ค๋ฉด lbu ์“ฐ๋ฉด ๋จ!
์–˜๋Š” zero extended๋ฅผ ์”€
์•Œ์•„์„œ unsigned๋กœ ์ƒ๊ฐํ•˜๊ณ  ํŒŒ์•…ํ•จ
ex) FF = 000000FF = 255

4. sb

: register์— ์žˆ๋Š” ํ•œ byte(=8bit)๋ฅผ register์— writes

  • S type instruction

sb rs2, address

sb t0, -7(s3)
# [s3 + (-7)] <= t0[7:0]

sb๋Š” ๋ ˆ์ง€์Šคํ„ฐ์— ์ €์žฅ๋œ ๋ฐ์ดํ„ฐ์˜ LSB๋กœ๋ถ€ํ„ฐ ๊ฐ’์„ ๊ฐ€์ ธ์™€ memory์— ์“ด๋‹ค.

  • ๋ฉ”๋ชจ๋ฆฌ์˜ ๋‹จ์–ด์˜ ๋‹ค๋ฅธ bits๋“ค์€ ๊ฑด๋“ค์ง€ ์•Š๋Š”๋‹ค !! (no sign extension!)
  • ์™œ -7์„ imm ๋‘๊ฐœ์— ๋‚˜๋ˆ ์„œ ์ €์žฅํ•˜๋Š”๊ฐ€๋Š” ๊ทธ๋ƒฅ ํ˜•์‹์„ ๋งž์ถ”๊ธฐ ์œ„ํ•จ์ด์—ˆ๋‚˜... ์™ค๊นŒ ๊ธฐ์–ต์ด ์•ˆ๋‚˜

5. lui(Load Upper Immediate), auipc(Add Upper Immediate to PC)

  • U type instruction

lui๋Š” ๋’ค์— ์˜ค๋Š” 24bit ์ˆซ์ž๋ฅผ register์— ์ €์žฅํ•˜๋Š” ๊ฒƒ
auipc๋Š” ํ˜„์žฌ ๋ณด๊ณ  ์žˆ๋Š” instruction์˜ ์ฃผ์†Œ(=PC)๋กœ ๋ถ€ํ„ฐ ์ƒ์ˆ˜๋งŒํผ ๋”ํ•œ ์ˆซ์ž๋ฅผ ์ €์žฅํ•˜๋Š” ๊ฒƒ

lui rd, imm20
# rd = {imm20, 12'b0}

auipc rd,imm20
# rd = PC + {imm20, 12'b0}

lui ์™€ auipc๋Š” Not LSB!! ์–˜๋Š” ์˜ค๋ฅธ์ชฝ์— ๋ถ™์—ฌ๋„ฃ์ง€ ์•Š๊ณ  ์™ผ์ชฝ์— ๋ถ™์—ฌ๋„ฃ์€ ๋‹ค์Œ ์˜ค๋ฅธ์ชฝ์€ 0์œผ๋กœ ์ฑ„์›Œ์ค€๋‹ค.

ex) lui t0, 0x12345
-> t0 : 0x12345 | 0x000

auipc t0, 0x12345
-> t0 : (ํ˜„์žฌ PC) + 0x1234_5000

32 bit ์ƒ์ˆ˜๋ฅผ register์— ๋ถˆ๋Ÿฌ์˜ค๋ ค๋ฉด ?

  1. lw instruction ์‚ฌ์šฉ
  2. lui + addi instruction ์‚ฌ์šฉ
lui t0, 0x12345
addi t0, t0, 0x678

6. Pseudo Instructions

  • RISC-V๋Š” ์‹ค์ œ๋กœ ์žˆ๋Š” ๋ช…๋ น์–ด๋Š” ์•„๋‹ˆ์ง€๋งŒ ๊ทธ๋Ÿฐ ๋ช…๋ น์–ด๋“ค์„ ๋ช‡ ๊ฐœ์”ฉ ๋ฌถ์–ด์„œ ํ•œ ๋ฒˆ์— ํŽธํ•˜๊ฒŒ ์“ธ ์ˆ˜ ์žˆ๊ฒŒ ์ •์˜ํ•œ Pseudo instructions์„ ์ œ๊ณตํ•œ๋‹ค!

  • li : 32bit ์ƒ์ˆ˜๋ฅผ s0 ๋ ˆ์ง€์Šคํ„ฐ์— load
  • la : op1์˜ ์ฃผ์†Œ๊ฐ’์„ s0 ๋ ˆ์ง€์Šคํ„ฐ์— load
  • mv : s1 ๊ฐ’์„ s2์— ๋ณต์‚ฌ ๋ถ™์—ฌ๋„ฃ๊ธฐ (์˜ฎ๊ธฐ๊ธฐ)
  • nop : ๋ง๊ทธ๋Œ€๋กœ ์•„๋ฌด๊ฒƒ๋„ ์•ˆํ•˜๋Š”.. (์™œ ์žˆ๋Š”๊ฑธ๊นŒ)